This invention relates to the utilization of FLASH memories.
FLASH memories are relatively recent devices which have the electrical erase capability of an EEPROM (Electrically Erasable and Programmable Read Only Memory), but with a higher density and lower cost since they generally comprise a single MOS device per cell.
In a typical use of a FLASH device for nonvolatile storage (i.e., information is retained through power outages), a predetermined number of rows or columns of cells can be erased and rewritten to store new data. One drawback of such devices is that repeated erasures of the same cells can result in permanent failure of the MOS devices constituting those cells as, for example, when the floating gate of the MOS device develops a permanent positive potential which keeps the cell always "ON". (For a discussion of FLASH memories see, for example, U.S. Pat. No. 5,126,808 issued to Montalvo et al.)
In standard EEPROM devices, it has been proposed to extend the life of the memory by dividing the total memory into banks with some locations reserved for bank pointers. After a certain number of write cycles in one bank, the data is moved to another bank and the bank pointer is incremented to indicate the bank now in use. (See Kannan, "Technique Extends EEPROM Life," EDN, p. 275 (Nov. 7, 1991).